PALs for IEEE 696

1985 — Megasys (A Robert E. Weatherford D/B/A)

A set of interface chips for the IEEE 696 bus, implemented in 16L8, 16R4, and 16R8 series PALs. These parts were to be used in next-generation S-100 bus designs of "slave" CPU boards and high performance block memory co-processors.

Click on a part number to see the datasheet.

16L801A — IEEE 696.
The 16L801A contains the necessary logic to perform priority compares on the IEEE 696 DMA arbitration bus.
16L802 — IEEE 696.
The 16L802 provides an interface between the Z80 and the IEEE 696 status bus. Two disable pins are provided for the high current three-state output drivers along with a transparent latch for the status word.
16R401A — Z80 Code Segment Decoder.
The 16R401A generates a Code Segment output for the Z80 instruction set.
16R801 — IEEE 696.
The 16R801 provides all IEEE 696 bus timing signals for temporary masters, with the exception of pSTVAL.
16R802 — IEEE 696.
The 16R802 coupled with the 16R801 IEEE 696 Bus State Sequencer and the 16L801A IEEE 696 DMA Priority Comparator form the heart of a high performance DMA controller for the IEEE 696 bus.

A proposal for an IEEE 696 Multi-master protocol was written, extending the existing temporary bus master protocol.

IEEE 696 Bus Multi-master Protocol

Intent

This document represents an addition to the IEEE 696 (S-100) bus specification. Its purpose is to provide a standardized protocol for handling multiple permanent bus masters. With the current IEEE 696 specification, it is impossible to have multiple processors on a common bus that run at different clock rates. The multi-master protocol will allow up to sixteen permanent masters to share the bus (the number of temporary masters is reduced to fifteen) regardless of the clock rate of any individual permanent master. The switchover from one permanent master to another actually places the new clock on the bus in a synchronous, glitchless manner.

Overview

Permanent masters are assigned an address from zero to fifteen, similar to the DMA priority assignments. One master is assigned as the power-up master. Only the power-up master may take control of the bus after a reset operation. The power-up master is assigned address zero. Masters not currently on the bus are in a "sleep" state. In the sleep state, a master's bus drivers are three-stated, regardless of the levels on ADSB, CDSB, DODSB, or SDSB, its clock is three-stated, and the processor is in either a hold or reset state. Permanent bus master selection is accomplished via the master select controller through a single 8 bit I/O port. An output write to this port will select a given master. An input read from this port will return the current master. The low four bits of the value determine the address of the master.

Hardware Requirements

The hardware to implement the multi-master protocol can be divided into two sections, the hardware required for each master on the bus, and the hardware for the master select controller.

The extra hardware needed for each master is minimal. Three or four packages is all that is generally required. The function of each master is to decode its address, implement the sleep state and synchronously enable its clock onto the bus. A sample implementation is given at the end of this document.

The master select controller hardware consists of an I/O port and a state machine to synchronize the switchover operation. Only one master select port is required (and allowed) per bus. Implementation of this hardware on a processor board is acceptable, but not recommended. A sample stand-alone implementation is given at the end of this document.

Special Bus Signal Usage

One new signal, PSEL is required and should be capable of occupying any of the NDEF or RFU pins for now, until a standard bus pin number is agreed upon.

Description of Protocol

A master switchover operation is initiated by an output write to the master select port. As soon as the output write cycle is detected (logic equation: [ SOUT * pSync * (A0-A7 = port address) ] ¯ pSTVAL), HOLD is asserted, along with priority 15 (DMA0 - DMA3 = low) to immediately suspend operation of the current master after the end of the output write cycle. NOTE: This can potentially violate section 2.8.3.2.1 of the IEEE 696 bus arbitration protocol, as a temporary master may this that is has already won the bus. However, the new priority assertion by the master select controller will always be higher, and will occur early enough to kick any requester off the bus long enough before HLDA goes active.

On the rising edge of HLDA, after one t_set delay (F falling), the low four bits from the processor select port are placed onto the DMA arbitration bus (DMA0 through DMA3), and the control bus is driven as follows:

Signal    Logic State    Electrical Level

pSync    F L

pSTVAL    F H

pDBIN F L

pWR F H

pHLDA T H

On the next rising edge of the clock, PSEL (new signal) is asserted. At this point, the previously active bus master disconnects its clock from the bus. Three-stating the clock after its rising edge ensures that no glitching occurs, and the clock remains at a high level. The leading edge of PSEL also activates the bus master whose address corresponds with the address on the DMA arbitration bus, and that master exits the sleep state. Once a bus master exits the sleep state, it waits for a rising edge on its clock, at which time it enables its clock (along with the other bus signals) onto the bus. Enabling the clock after its low to high transition ensures a clean switchover from one bus master's clock to another's, and eliminates the possibility of contention between bus drivers.

On the next falling edge of the new clock, all control signals (HOLD, PSEL, the arbitration bus, and the control bus) previously asserted are removed.